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toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 0 toshiba nand memory toggle ddr1.0 technical data sheet rev. 0.2 2012 ? 03 ? 01 toshiba semiconductor & storage products memory division
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 1 contents 1. introduct ion ............................................................................................................................................. 5 1.1. general desc ription ............................................................................................................ .......................... 5 1.2. definitions and abbrevia tions.................................................................................................. .................... 5 1.3. features ....................................................................................................................... ................................. 7 1.4. diagram legend............................................................................................................................................ 8 2. physical in terfac e.................................................................................................................................. 9 2.1. pin descri ptions............................................................................................................... ............................. 9 2.2. pin assignment (top vi ew) ...................................................................................................... ........ 10 2.3. block di agram ..................................................................................................................................... 11 2.4. independent da ta buses ......................................................................................................... ................... 12 2.5. absolute maximu m dc ra ting .................................................................................................................. 12 2.6. operating temperat ure cond ition................................................................................................ ............. 13 2.7. recommended operat ing cond itions............................................................................................... .......... 13 2.8. valid blocks................................................................................................................... .............................. 13 2.9. ac overshoot/undersh oot requir ements........................................................................................... ....... 14 2.10. dc operating ch aracteristics................................................................................................... ................. 15 2.11. input/output capacitance (t oper =25 , f=1mhz) ................................................................................... 17 2.12. dq driver strength ............................................................................................................. ....................... 17 2.13. input/output slew rate ......................................................................................................... ..................... 19 2.14. r/ b and sr[6] re lation ship........................................................................................................ ............. 21 2.15. write pr otect .................................................................................................................. ............................. 21 3. memory orga nization ............................................................................................................ .............. 22 3.1. addressing..................................................................................................................... .............................. 23 3.1.1. plane addr essing ............................................................................................................... ..................... 23 3.1.2. extended blocks arrangement .................................................................................................... .......... 24 3.2. factory defe ct ma pping ......................................................................................................... .................... 25 3.2.1. device requ iremen ts............................................................................................................ .................. 25 3.2.2. host requ irements .............................................................................................................. ................... 26 4. function de scription ........................................................................................................... ............... 27 4.1. discovery and in itializa tion ................................................................................................... .................... 27 4.1.1. single channe l discovery ....................................................................................................... ............... 27 4.1.2. dual channel discovery......................................................................................................... ................ 27 4.2. mode sele ction ................................................................................................................. ........................... 29 4.2.1. toggle ddr1.0 ge neral timing ................................................................................................... .......... 30 4.2.1.1. command latc h cycle............................................................................................................ ................ 30 4.2.1.2. address latc h cycle ............................................................................................................ ................... 30 4.2.1.3. basic data in put ti ming ........................................................................................................ ................ 31 4.2.1.4. basic data ou tput ti ming ....................................................................................................... .............. 32 4.2.1.5. read id op eratio n.................................................................................................................................. 33 4.2.1.6. status read cycle.............................................................................................................. ..................... 34 4.2.1.7. set feat ure ............................................................................................................................................. 35 4.2.1.8. get feat ure ............................................................................................................................................. 35 4.2.1.9. page read operat ion ............................................................................................................ .................. 36 4.2.1.10. page program operat ion......................................................................................................... ........... 37 4.2.2. sdr genera l timing ............................................................................................................. ................. 38 4.2.2.1. command latc h cycle............................................................................................................ ................ 38 4.2.2.2. address latc h cycle ............................................................................................................ ................... 38 4.2.2.3. basic data in put ti ming ........................................................................................................ ................ 39 4.2.2.4. basic data ou tput ti ming ....................................................................................................... .............. 39 4.2.2.5. read id op eratio n.................................................................................................................................. 40 4.2.2.6. status read cycle.............................................................................................................. ..................... 40 4.2.2.7. set feat ure ............................................................................................................................................. 41 4.2.2.8. get feat ure ............................................................................................................................................. 41 4.2.2.9. page read operat ion ............................................................................................................ .................. 42 4.2.2.10. page program operat ion......................................................................................................... ........... 43 4.3. ac timing char acterist ics ......................................................................................................................... 44 4.3.1. timing parameters description.................................................................................................. ........... 44 4.3.2. timing parame ters t able........................................................................................................ ............... 46 5. command description an d device operati on .......................................................................... 49
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 2 5.1. basic comm and sets ............................................................................................................. ..................... 49 5.2. basic oper ation................................................................................................................ ........................... 50 5.2.1. page read operat ion ............................................................................................................ .................. 50 5.2.1.1. page read operation with random da ta output................................................................................. 50 5.2.1.2. data out after status read ................................................................................................................... 51 5.2.2. sequential cache read oper ation ................................................................................................ ......... 51 5.2.3. random cache re ad oper ation .................................................................................................... ......... 52 5.2.4. page program operat ion ......................................................................................................... ............... 52 5.2.4.1. program operation with random data input ...................................................................................... 52 5.2.5. cache program operat ion........................................................................................................ .............. 53 5.2.6. block erase operat ion.......................................................................................................... .................. 53 5.2.7. copy-back progra m operat ion .................................................................................................... .......... 54 5.2.7.1. copy-back program operation with random data in put.................................................................... 54 5.2.8. set feature operat ion.......................................................................................................... .................. 55 5.2.8.1. driver strength setting (10h) .................................................................................................. ............... 56 5.2.9. get feature operat ion .......................................................................................................... ................. 56 5.2.10. read id op eratio n.................................................................................................................................. 57 5.2.10.1. 00h address id defini tion...................................................................................................... ............ 57 5.2.10.2. 40h address id defini tion...................................................................................................... ............ 58 5.2.11. read status operat ion .......................................................................................................... ................. 59 5.2.12. reset oper ation ................................................................................................................ ...................... 60 5.2.13. reset lun op eratio n ............................................................................................................................. 62 5.3. extended op eration............................................................................................................. ....................... 62 5.3.1. extended command sets .......................................................................................................... ............. 62 5.3.2. page copy (2 ) operat ion........................................................................................................ ................. 63 5.3.3. device identification table read operation..................................................................................... ..... 64 5.3.4. device identification table de finition ......................................................................................... .......... 65 5.3.5. read status enhanced ........................................................................................................................... 70 5.3.6. read lun #0 stat us operation ................................................................................................... .......... 71 6. application note s and co mments................................................................................................. . 72 7. package di mensions ............................................................................................................. .......................... 78 8. revision history............................................................................................................... ............................... 79
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 3 list of figures figure 1. bl ock diag ram .......................................................................................................................................... 11 figure 2. overshoot/u ndershoot diagram ......................................................................................... ..................... 14 figure 3. t rise and t fall definition for ou tput slew rate ...................................................................................... 20 figure 4. write protect timing requ irements of the pr ogram oper ation ........................................................... .... 21 figure 5. write protect timing requ irements of the erase oper ation ............................................................. ....... 21 figure 6. target organi zation .................................................................................................. ............................... 22 figure 7. row address layout ................................................................................................... .............................. 23 figure 8. position of plane address ............................................................................................ ............................. 23 figure 9. area marked in first or la st page of block indicating defect ......................................................... .......... 25 figure 10. flow chart to creat e initial invalid block table .................................................................... ................. 26 figure 11. initia lization timing............................................................................................... ................................ 28 figure 12. command latch cycl e timing.......................................................................................... ..................... 30 figure 13. address latch cycl e timing .......................................................................................... ........................ 30 figure 14. basic da ta input timing............................................................................................. ........................... 31 figure 15. basic da ta output timing ............................................................................................ ......................... 32 figure 16. read id operatio n timing............................................................................................ ......................... 33 figure 17. status read cycl e timing ............................................................................................ .......................... 34 figure 18. set feature timing.................................................................................................. ............................... 35 figure 19. get feature timing .................................................................................................. .............................. 35 figure 20. page read operatio n timing .......................................................................................... ....................... 36 figure 21. read hold operation with ce high..................................................................................................... 36 figure 22. page prog ram operatio n timing ....................................................................................... .................... 37 figure 23. command latch cycl e timing.......................................................................................... ..................... 38 figure 24. address latch cycl e timing .......................................................................................... ........................ 38 figure 25. basic da ta input timing............................................................................................. ........................... 39 figure 26. basic da ta output timing ............................................................................................ ......................... 39 figure 27. read id operatio n timing............................................................................................ ......................... 40 figure 28. status read cycl e timing ............................................................................................ .......................... 40 figure 29. set feature timing.................................................................................................. ............................... 41 figure 30. get feature timing .................................................................................................. .............................. 41 figure 31. page read operatio n timing .......................................................................................... ....................... 42 figure 32. page prog ram operatio n timing ....................................................................................... .................... 43 figure 33. page read timing.................................................................................................... ............................... 50 figure 34. page read with random data ou tput timing ............................................................................ ......... 50 figure 35. data out afte r status read timing ................................................................................... ................... 51 figure 36. sequential cache read timing.............................................................................................................. 51 figure 37. random cache read timing ............................................................................................ ...................... 52 figure 38. page program timing................................................................................................. ............................ 52 figure 39. program operation wi th random data input timing ..................................................................... ..... 52 figure 40. cache program timing................................................................................................ ........................... 53 figure 41. bloc k erase timing .................................................................................................. .............................. 53 figure 42. copy-back program timing ............................................................................................ ....................... 54 figure 43. copy-back program wi th random data input timing ..................................................................... ... 54 figure 44. set feature timing.................................................................................................. ............................... 55 figure 45. get feature timing .................................................................................................. .............................. 56 figure 46. read id timing ...................................................................................................... ................................ 57 figure 47. read status timing .................................................................................................. .............................. 59 figure 48. re set ti ming........................................................................................................ .................................... 60 figure 49. reset timing du ring program operation............................................................................... ................. 60 figure 50. reset timing during erase operat ion................................................................................. .................... 60 figure 51. reset timing during read operation.................................................................................. .................... 60 figure 52. status read after reset operation ................................................................................... ...................... 61 figure 53. successive reset op eration.......................................................................................... ........................... 61 figure 54. single lun reset timing ............................................................................................. ......................... 62 figure 55. example timing with page copy (2) ................................................................................... .................. 63 figure 56. device identifi cation table read timing ............................................................................. ................. 64 figure 57. read status timing .................................................................................................. .............................. 70 figure 58. read l un#0 status timing............................................................................................ ....................... 71
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 4 list of tables table 1 pin descriptions ............................................................................................................................................ 9 table 3 absolute maximum rating .......................................................................................................................... 12 table 4 operating temperature condition ............................................................................................................... 13 table 5 recommended operating condition ........................................................................................................... 13 table 6 valid blocks ................................................................................................................................................. 13 table 7 ac overshoot/undershoot specification ..................................................................................................... 14 table 8 dc & operating characteristics for toggle vccq=3.3v .............................................................................. 15 table 9 dc & operating characteristics for toggle vccq=1.8v .............................................................................. 16 table 10 dc & operating characte ristics for sdr vccq=1.8v and 3.3v .............................................................. 17 table 11 input/ output capacitance ......................................................................................................................... 17 table 12 dq drive strength settings ....................................................................................................................... 17 table 13 testing conditions for impedance values ................................................................................................. 17 table 14 output drive strength impedance values ................................................................................................. 18 table 15 pull-up and pull-down output impedance mismatch ................................................................................ 18 table 16 derating factor .......................................................................................................................................... 19 table 17 input slew rate ......................................................................................................................................... 19 table 18 testing conditions for input slew rate ..................................................................................................... 19 table 19 output slew rate requirements ............................................................................................................... 19 table 20 testing conditions for output slew rate .................................................................................................. 20 table 21 the addressing of this device. .................................................................................................................. 23 table 23 toggle ddr1.0 interface mode selection ................................................................................................. 29 table 24 sdr interface mode selection .................................................................................................................. 29 table 25 timing parameters description ................................................................................................................. 44 table 26 ac timing charateristics ........................................................................................................................... 46 table 27 ac test conditions .................................................................................................................................... 48 table 28 read/program/erase timing characteristics ............................................................................................ 48 table 29 basic command sets ............................................................................................................................... . 49 table 30 set feature addresses ............................................................................................................................... 55 table 31 driver strength setting data ..................................................................................................................... 56 table 32 interface change setting data ................................................................................................................... 56 table 33 00h address id definition table ................................................................................................................ 57 table 35 3rd id data ................................................................................................................................................ 57 table 36 4th id data ................................................................................................................................................ 57 table 38 6th id data ................................................................................................................................................ 58 table 39 40h address id cycle ............................................................................................................................... 58 table 40 40h address id definition ......................................................................................................................... 58 table 41 read status definition for 70h .................................................................................................................. 59 table 42 read status definition for 71h .................................................................................................................. 59 table 43 extended command sets ......................................................................................................................... 62 table 44 parameter page definitions ...................................................................................................................... 65 table 45 read status enhanced definition ............................................................................................................. 70 table 46 read lun#0 status definition .................................................................................................................. 71
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 5 1. introduction 1.1. general description toggle ddr is a nand interface for high performance applications which support data read and write operations using bidirectional dqs. toggle ddr nand has implemented ?double data rate? with out a clock. it is compatible with functions and command which have been supported in conventional type nand(i.e. sdr nand) while providing high data transfer rate based on the high-sp eed toggle ddr interface and saving po wer with separated dq voltage. for applications that require high capacity and high perfor mance nand, toggle ddr nand is the most appropriate. toggle ddr1.0 nand supports the interface speed of up to 1 00 mhz, which is faster than the data transfer rate offered by sdr nand. toggle ddr nand transfers data at high speed using dqs signal that behaves as a clock, and dqs shall be used only when data is transferred for optimal power consumption. this device supports both sdr interfac e and toggle ddr interface. when starti ng, the device is activated in sdr mode. the interface mode can be changed into toggle ddr in terface utilizing specific command issued by the host. 1.2. definitions and abbreviations sdr acronym for single data rate. ddr acronym for double data rate. address the address is comprised of a column address with 2 cycles and a row a ddress with 3 cycles. the row address identifies the page, block and lun to be accessed. the colu mn address identifies the byte within a page to access. the least significant bit of the column address shall always be zero. column the byte location within the page register. row refer to the block and page to be accessed. page the smallest addressable unit for th e read and the program operations. block consists of multiple pages and is the smalle st addressable unit for the erase operation. plane the unit that consists of a number of blocks . there are one or more planes per lun. page register register used to transfer data to and from the flash array. cache register register used to transfer data to and from the host. defect area the defect area is where factory defects are marked by the manufacturer. refer to the section 3.2 device the packaged nand unit. a device may contain more than a target.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 6 lun (logical unit number) the minimum unit that can independently execute commands and report status. there are one or more luns per ce . target an independent nand flas h component with its own ce signal. sr[x] (status read) sr refers to the status register contained within a particul ar lun. sr[x] refers to bit x in the status register for the associated lun. refer to section 5.13 for the defi nition of bit meanings wi thin the status register.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 7 1.3. features organization part number tc58teg5dcj tc58teg5dcjta00 (t oper : 0 70) TC58TEG5DCJTAI0 (t oper : -40 +85 ) device capacity 17664 ? 256 ? 1060 ? 8 bits page size 17664 bytes block size (4m ? 320 k) bytes plane size 2396651520 bytes plane per one lun 1 planes lun per one target 1 luns target per one device 1 targets ? modes basic operation page read operation (with random data output), data out after stat us read, sequential cache read operation, random cache read operation, page program operat ion (with random data input), cache program operation, block eras e operation, copy-back program oper ation (with random data input), set feature operation, get feature operation, read id operation, read status operation, reset operation, reset lun operation extend operation page copy (2) operation, device iden tification table read operation, read status enhanced operation, read lun #0 status operation ? mode control serial input/output command control ? power supply v cc ? 2.7 v to 3.6 v v ccq = 2.7 v to 3.6 v / 1.7 v to 1.95v
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 8 ? access time cell array to register 100 ? s max (tentative) 50 ? s typ. (tentative) data transfer rate 100 mhz ? program/erase time auto page program 1400 ? s/page typ. (tentative) auto block erase 5 ms/block typ. (tentative) ? operating current read tbd ma max. (per 1 chip) program (avg.) tbd ma max. (per 1 chip) erase (avg.) tbd ma max. (per 1 chip) standby tbd ? a max. (per 1 chip) ? package (weight: tbd g typ.) ? reliability refer to application notes and comments. 1.4. diagram legend diagrams in the toggle ddr1.0 datasheet use the following legend: command this legend shows the command data. refer to the table 29 for more information about the command data. address c1 c2 r1 r2 r3 this legend shows the address data. the addresses are comprised of 2 cycles column address and 3 cycles row address. c1: column address 1 c2: column address 2 r1: row address 1 r2: row address 2 r3: row address 3 w-data this legend shows host writing data (data input) to the device. r-data this legend shows host reading data (data output) from the device. sr[x] this legend shows host reading the status register within a particular lun.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 9 2. physical interface 2.1. pin descriptions table 1 pin descriptions sdr toggle ddr1.0 pin function dq[7:0] dq[7:0] data inputs/outputs the dq pins are used to input command, address and data and to output data during read operations. the dq pins float to high-z when the chip is deselected or when the outputs are disabled. cle cle command latch enable the cle input controls the activating path for comm ands sent to the command register. when active high, commands are latched into the command register through the dq ports on the rising edge of the we signal. ale ale address latch enable the ale input controls the activating path fo r address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. re re read enable the re input is the serial data-out control, and when active, drives the data onto the dq bus. data is valid after t dqsre of rising edge & falling edge of re , which also increments the internal column address counter by each one. we we write enable the we input controls writes to the dq port. commands, addresses are latched on the rising edge of the we pulse. wp wp write protect the wp pin provides inadvertent program/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/ b r/ b ready/busy output the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. - dqs data strobe output with read data, input with write data. edge-aligned with read data, centered in write data. vcc vcc power vcc is the power supply for device. vccq vccq dq power the vccq is the power supply for input and/or output signals. vss vss ground vssq vssq dq ground the vssq is the power supply ground nc nc no connection ncs are not internally connected. they can be driven or left unconnected. nu nu not use nus must be left unconnected. note: 1) connect all vcc and vss pins of each device to common power supply outputs. 2) do not leave all vcc, vccq, vss and vssq disconnected.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 10 vss nc vssq vccq dq7 dq6 dq5 dq4 vssq vccq vccq v cc v ss dqs vccq vssq dq3 dq2 dq1 dq0 vccq vssq nc vss 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 vcc vss nc nc nc nc by/ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc vss vcc vss nc nu or vssq nu or vccq dq7 dq6 dq5 dq4 nu or vssq nu or vccq vccq v cc v ss nu vccq nu or vssq dq3 dq2 dq1 dq0 nu or vccq nu or vssq nc vss vcc vss nc nc nc nc by/ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc vss vcc 2.2. pin assignment (top view) sdr/toggle ddr1.0 tx58teg5dcj sdr only sdr/toggle ddr1.0 sdr only
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 11 2.3. block diagram figure 1. block diagram i/o control circuit status register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control by/ry v cc dq0 v ss dq7 ce cle ale we re by/ry row address buffer decoder to wp address register d q s dqs v ccq v ssq
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 12 2.4. independent data buses there may be two independent 8-bit data buses in some packages, with two, four or eight ce signals. if the device supports two independent data buses, then ce 1, ce 3, ce 5, and ce 7 (if connected) shall use the second data bus. ce 0, ce 2 ce 4, and ce 6 shall always use the first data bus pins. note that all ce s may use the first data bus and the first set of control signals ( re 0, cle0, ale0, we 0, and wp 0) if the device does not support independent data buses. table 2 defines the control signal to ce signal mapping when th ere are two independent x8 data buses. table 2 dual channel(x8) data bus signal to ce mapping signal name ce r/ b 0 ce 0, ce 4 r/ b 1 ce 1, ce 5 r/ b 2 ce 2, ce 6 r/ b 3 ce 3, ce 7 re 0 ce 0, ce 2, ce 4, ce 6 re 1 ce 1, ce 3, ce 5, ce 7 cle0 ce 0, ce 2, ce 4, ce 6 cle1 ce 1, ce 3, ce 5, ce 7 ale0 ce 0, ce 2, ce 4, ce 6 ale1 ce 1, ce 3, ce 5, ce 7 we 0 ce 0, ce 2, ce 4, ce 6 we 1 ce 1, ce 3, ce 5, ce 7 wp 0 ce 0, ce 2, ce 4, ce 6 wp 1 ce 1, ce 3, ce 5, ce 7 dqs0 ce 0, ce 2, ce 4, ce 6 dqs1 ce 1, ce 3, ce 5, ce 7 implementations may tie the data lines and control signals ( re , cle, ale, we , wp , and dqs) together for the two independent 8-bit data buses externally to the device. 2.5. absolute maximum dc rating stresses greater than those listing in table 3 may cause permanent damage to the device. this is a stress rating only . operation beyond the operating conditions specified in table 4 is not recommended. extended exposure beyond these conditions may affect device reliability. table 3 absolute maximum rating parameter symbol rating unit vcc -0.6 to +4.6 vccq(3.3v) -0.6 to +4.6 vin vccq(1.8v) -0.2 to +2.4 vccq(3.3v) -0.6 to +4.6 voltage on any pin relative to vss vi/o vccq(1.8v) -0.2 to +2.4 v
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 13 2.6. operating temperature condition table 4 operating temperature condition symbol parameter part number rating unit operating temperature range for commercial tc58teg5dcjta00 0 70 toper operating temperature range for industrial TC58TEG5DCJTAI0 -40 +85 t solder soldering temperature (10 s) 260 t stg storage temperature -55 +150 note: 1) operating temperature (t oper ) is the case surface temperature on the center/top side of the nand. 2) operating temperature range specif ies the temperatures where all nand specifications will be supported. during operation, the nand case temp erature must be maintained between th e range specified in the table under all operating conditions. 2.7. recommended operating conditions table 5 recommended operating condition parameter symbol min typ. max unit supply voltage vcc 2.7 3.3 3.6 v ground voltage vss 0 0 0 v supply voltage for 1.8v i/o signaling vccq 1.7 1.8 1.95 v supply voltage for 3.3v i/o signaling vccq 2.7 3.3 3.6 v ground voltage for i/o signaling vssq 0 0 0 v vccq and vcc may be distinct and unique voltages. the device shall support one of the following vccq/vcc combinations, vcc = 3.3v, vccq = 3.3v vcc = 3.3v, vccq = 1.8v all parameters, timing modes and other characteristics are related to the supported voltage combination. 2.8. valid blocks table 6 valid blocks part number min max unit tc58teg5dcj 1009 1060 blocks note: 1) the device occasionally contains unusable blocks. 2) the first block (block 0) is guaranteed to be a valid block at the time of shipment. 3) the specification for the minimum number of valid blocks is applicable over the device lifetime. 4) the number of valid blocks includes extended blocks.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 14 2.9. ac overshoot/undershoot requirements the device may have ac overshoot or und ershoot from vccq and vssq levels. table 7 defines the maximum values that the ac overshoot or un dershoot may attain. these values apply for both 3.3v and 1.8v vccq levels. table 7 ac overshoot/undershoot specification maximum value parameter 67~100mhz unit max. peak amplitude allowed for overshoot area 1 v max. peak amplitude allowed for undershoot area 1 v max. overshoot area above vccq 1.8 v*ns max. undershoot area above vssq 1.8 v*ns note: 1) this specification is intended for devices with no clamp protection and is guaranteed by design. figure 2. overshoot/undershoot diagram volts (v) undershoot area maximum a mplitude vssq overshoot area vccq maximum a mplitude
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 15 2.10. dc operating characteristics table 8 dc & operating characte ristics for toggle vccq=3.3v parameter symbol test conditions min typ max unit page read operation current i cc1 - - - tbd page program operation current i cc2 - - - tbd erase operation current i cc3 - - - tbd dq burst read current for vcc i cc4r t rc = t rc (min.), half data switchiing - - 80 dq burst write current for vcc i cc4w t dsc = t dsc (min.) half data switching - - 80 ma dq burst read current for vccq i ccq4r t rc = t rc (min.) half data switching, cload=0pf, nominal driver strength - - 50 dq burst write current for vccq i ccq4w t dsc = t dsc (min.) half data switching - - 10 bus idle current i cc5 - - - tbd stand-by current(cmos) i sb ce =vccq-0.2, wp =0v/vccq - - tbd input leakage current i li v in =0 to vccq(max) - - 10 output leakage current i lo v out =0 to vccq(max) - - 10 a ac input high voltage v ih (ac) - 0.8 xvccq - note 5) dc input high voltage v ih (dc) - 0.7 xvccq - vccq +0.3 ac input low voltage v il (ac) - note 5) - 0.2 xvccq dc input low voltage v il (dc) - -0.3 - 0.3 xvccq output high voltage level v oh i oh =-400 a 2.4 - - output low voltage level v ol i ol = 2.1ma - - 0.4 v output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - ma note: 1) typical value is measured at vcc=3.3v, t oper =25 . not 100% tested. 2) v oh and v ol should be available on these two conditions; ou tput strength is nominal and vccq=3.3v, rpd/rpu are all vccqx0.5. if the drive strength settings are supported, table 12 shall be used to derive the output driver impedance values. 3) icc1,2 are without data cache. 4) icc1/2/3, i sb are the value of one chip, and an unselected chip is in standby mode. 5) refer to ac overshoot an d undershoot requirements.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 16 table 9 dc & operating characte ristics for toggle vccq=1.8v parameter symbol test conditions min typ max unit page read operation current i cc1 - - - tbd page program operation current i cc2 - - - tbd erase operation current i cc3 - - - tbd dq burst read current for vcc i cc4r t rc = t rc (min.) half data switchiing - - 80 dq burst write current for vcc i cc4w t dsc = t dsc (min.) half data switching - - 80 ma dq burst read current for vccq i ccq4r t rc = t rc (min.) half data switching cload=0pf, nominal driver strength - - 50 dq burst write current for vccq i ccq4w t dsc = t dsc (min.) half data switching - - 10 bus idle current i cc5 - - - tbd stand-by current(cmos) i sb ce =vccq-0.2, wp =0v/vccq - - tbd input leakage current i li v in =0 to vccq(max) - - 10 output leakage current i lo v out =0 to vccq(max) - - 10 a ac input high voltage v ih (ac) - 0.8 xvccq - note 5) dc input high voltage v ih (dc) - 0.7 xvccq vccq +0.3 ac input low voltage v il (ac) - note 5) - 0.2 xvccq dc input low voltage v il (dc) - -0.3 - 0.3 xvccq output high voltage level v oh i oh =-100 a vccq-0.1 - - output low voltage level v ol i ol = 100 a - - 0.1 v output low current(r/ b ) i ol (r/ b ) v ol =0.2v 3 4 - ma note: 1) typical value is measured at vcc=3.3v, t oper =25 . not 100% tested. 2) v oh and v ol should be available on these two conditions; ou tput strength is nominal and vccq=1.8v, rpd/rpu are all vccqx0.5. if the drive st rength settings are supported, table 12 shall be used to derive the output driver impedance values. 3) icc1,2 are without data cache. 4) icc1/2/3, i sb are the value of one chip, and an unselected chip is in standby mode. 5) refer to ac overshoot an d undershoot requirements.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 17 table 10 dc & operating characteristics for sdr vccq=1.8v and 3.3v parameter symbol test conditions min typ max unit input leakage current i il v in ? 0 v to v cc ? ? ? 10 output leakage current i lo v out ? 0 v to v cc ? ?? ? 10 a power on reset current i cco0 *1 ce ? v il ? ? tbd read mode current i cco1 *2 ce ? v il , i out ? 0 ma, tcycle ? 25 ns ? ? tbd auto page program current i cco2 *2 ? ? ? tbd auto block erase current i cco3 ? ? ? tbd ma standby current i ccs ce ? v cc ? 0.2 v, wp ? 0 v/v cc , ? ? tbd a high level output voltage v oh i oh ? ? 0.4 ma (2.7 v ? v cc ? 3.6 v) 2.4 ? ? low level output voltage v ol i ol ? 2.1 ma (2.7 v ? v cc ? 3.6 v) ? ? 0.4 v output current of by/ ry pin i ol ( by/ ry ) v ol ? 0.4 v (2.7 v ? v cc ? 3.6 v) ? 8 ? ma note: 1)*1: icco0 is the average current during r/b signal=?busy? state . 2)*2: all operation current are without data cache. 2.11. input/output capacitance (t oper =25 , f=1mhz) table 11 input/ output capacitance symbol parameter test condition min max unit c in input v in =0v - 10 pf c out output v out =0v - 10 pf 2.12. dq driver strength the device may be configured with multiple driver strengths with ?set feature? command. there are underdrive, nominal, overdrive 1 option s. the toggle ddr1.0 supports all four driver strength settings. devices that support driver strength settings sha ll comply with the output driver requir ements in this section. a device is only required to meet driver strength values for either 3.3v vccq or 1.8v vccq, and is not required to meet driver strength values for both 3.3v vccq and 1.8v vccq. table 12 dq drive strength settings setting driver strength vccq overdrive 1 1.4x = 25 ohms nominal 1.0x = 35 ohms underdrive 0.7x = 50 ohms 3.3 v overdrive 1 1.4x = 25 ohms nominal 1.0x = 35 ohms underdrive 0.7x = 50 ohms 1.8 v the impedance values corresponding to seve ral different vccq values are defined in table 14 for 3.3v and 1.8v vccq. the test conditions that shall be used to verify the impedance va lues are specified in table 13 . the terms t oper (min) and t oper (max) are in reference to the minimum and ma ximum operating temperature defined for the device. table 13 testing conditions for impedance values condition temperature vccq (3.3v) vccq (1.8v) process minimum impedance toper (min) degrees celsius 3.6 v 1.95 v fast - fast nominal impedance 25 degrees celsius 3.3 v 1.8 v typical maximum impedance toper (max) degrees celsius 2.7 v 1.7 v slow-slow
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 18 table 14 output drive strength impedance values minimum nominal maximum output strength rpd/rpu vout to vssq vccq(3.3v) vccq(1.8v) vccq(3.3v) vccq(1.8v) vccq(3.3v) vccq(1.8v) units vccq 0.2 8.0 10.5 15.0 19.0 30.0 44.0 ohms vccq 0.5 15.0 13.0 25.0 25.0 45.0 47.0 ohms rpd vccq 0.8 20.0 16.0 35.0 32.5 65.0 61.5 ohms vccq 0.2 20.0 16.0 35.0 32.5 65.0 61.5 ohms vccq 0.5 15.0 13.0 25.0 25.0 45.0 47.0 ohms overdrive1 rpu vccq 0.8 8.0 10.5 15.0 19.0 30.0 44.0 ohms vccq 0.2 12.0 15.0 22.0 27.0 40.0 62.5 ohms vccq 0.5 20.0 18.0 35.0 35.0 65.0 66.5 ohms rpd vccq 0.8 25.0 22.0 50.0 52.0 100.0 88.0 ohms vccq 0.2 25.0 22.0 50.0 52.0 100.0 88.0 ohms vccq 0.5 20.0 18.0 35.0 35.0 65.0 66.5 ohms nominal rpu vccq 0.8 12.0 15.0 22.0 27.0 40.0 62.5 ohms vccq 0.2 18.0 21.5 32.0 39.0 55.0 90.0 ohms vccq 0.5 29.0 26.0 50.0 50.0 100.0 95.0 ohms rpd vccq 0.8 40.0 31.5 75.0 66.5 150.0 126.5 ohms vccq 0.2 40.0 31.5 75.0 66.5 150.0 126.5 ohms vccq 0.5 29.0 26.0 50.0 50.0 100.0 95.0 ohms underdrive rpu vccq 0.8 18.0 21.5 32.0 39.0 55.0 90.0 ohms table 15 pull-up and pull-down output impedance mismatch drive strength minimum maximum unit overdrive 1 0.0 8.8 ohms nominal 0.0 12.3 ohms underdrive 0.0 17.5 ohms note: 1) mismatch is the absolute value between pull-up and pull-down impedances. both are measured at the same temperature and voltage. 2) test conditions: vccq = vccq(min), vout = vccq 0.5
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 19 2.13. input/output slew rate the input slew rate requirem ents that the device shall comply with are defined in, table 16 , and table 17 . the output slew rate requirements that the devi ce shall comply with are defined in table 19 . the testing conditions that shall be used to verify the input slew rate and output slew rate are listed in table 18 and table 20 respectively. table 16 derating factor up to 100mhz input slew rate 3.3vccq 1.8vccq unit 1.0v/ns 0 0 0.8v/ns 332 180 0.6v/ns 884 482 ps note: 1) derating factor listed in this tabl e shall be applied to data setup time (tds) and data hold time (tdh) as additional value if the slew rate is less than the minimum value defined in table 17 . table 17 input slew rate minimum slew rate vccq up to 100mhz 3.3v 1.0v/ns 1.8v 1.0v/ns table 18 testing conditions for input slew rate parameter value positive input transition vil (dc) to vih (ac) negative input transition vih (dc) to vil (ac) table 19 output slew rate requirements vccq=3.3v vccq=1.8v parameter minimum maximum minimum maximum unit overdrive 1 1.5 9.0 0.85 5.0 v/ns nominal 1.2 7.0 0.75 4.0 v/ns underdrive 1.0 5.5 0.60 4.0 v/ns note : 1) measured with a test load of 5pf connected to vssq. 2) the ratio of pull-up slew rate to pu ll-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 20 table 20 testing conditions for output slew rate parameter value v ol (dc) 0.3 * vccq v oh (dc) 0.7 * vccq v ol (ac) 0.2 * vccq v oh (ac) 0.8 * vccq positive output transition v ol (dc) to v oh (ac) negative output transition v oh (dc) to v ol (ac) t rise (1) time during rising edge from v ol (dc) to v oh (ac) t fall (1) time during falling edge from v oh (dc) to v ol (ac) output slew rate rising edge (v oh (ac) - v ol (dc)) / t rise output slew rate falling edge (v oh (dc) - v ol (ac)) / t fall output capacitive load 50 ohms to vtt (vtt=0.5*vccq) note : 1) refer to figure 3. 2) output slew r ate is verified by design and characterization. it may not be subject to production test. 3) the minimum slew rate is the mini mum of the rising edge and the fallin g edge slew rate. the maximum slew rate is the maximum of the rising ed ge and the falling edge slew rate. figure 3. t rise and t fall definition for output slew rate t rise t fall v ol (dc) v ol (ac) v oh (ac) v oh (dc)
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 21 2.14. r/ b and sr[6] relationship r/ b represents the status of the selected target. r/ b goes busy when only a single lun is busy while rest of luns on the same target are idle. 2.15. write protect when wp is enabled, flash array is blocked from any program and erase operations. this signal shall only be transitioned when a target is idle. the host shall be allowed to issue a new command after t ww once wp is enabled. figure 4 describes the t ww timing requirement, shown with the start of a program command. and figure 5 shows with the star t of a erase command. 1. enable mode 2. disable mode figure 4. write protect timing requ irements of the program operation 1. enable mode 2. disable mode figure 5. write protect timing re quirements of the erase operation we dq[7:0] wp 80h 10h t ww min. 100ns we dq[7:0] wp 80h 10h t ww min. 100ns we dq[7:0] wp 60h d0h t ww min. 100ns we dq[7:0] wp 60h d0h t ww min. 100ns
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 22 3. memory organization a device contains one or more targ ets. a target is controlled by one ce signal. a target is organized into one or more logical units (luns). a logical unit (lun) is the minimum unit that can indepe ndently execute commands and report status. specifically, separate luns may operate on arbitrar y command sequences in parallel. for example, it is permissible to start a page program operation on lun 0 and then prior to the operation?s completion to start a read command on lun 1. a lun contains at least one page register and a flash a rray. the number of page re gisters is dependent on the number of plane operations supported for the lun. the flash array contains a number of blocks. a block is the smallest erasable unit of data within the fl ash array of a lun. there is no restriction on the number of blocks within the lun. a block contains a number of pages. a page is the smallest addressable unit for read and pr ogram operations. for targets that support partial page programming with constraints, the smallest addressable unit for program operations is a partial page. a page consists of a number of bytes. each lun shall have at least one page register. a page regist er is used for the temporary storage of data before it is moved to a page within the flash array or after it is moved from a page within the flash array. the byte location within the page register is referred to as the column. there are several mechanisms to achi eve parallelism within this architecture. there may be multiple commands outstanding to different luns at the same time. figure 6. target organization lun 0 ? plane 0 cache register page register block 0 page 0 page 1 page n-1 ? block m-2 page 0 page 1 page n-1 ?
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 23 3.1. addressing there are two address types used: the co lumn address and the row address. th e column address is used to access bytes within a page, i.e. the column address is the byte offset into the page. the least significant bit of the column address shall always be zero for a ddr interface, i.e. an even number of bytes is always transferred. the row address is used to address pages, bl ocks, and luns. when both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit address cycles. the row addresses follow in one or more 8-bit address cycles. ther e are some functions that may require only row addresses, such as block erase. in this case the column addresses are not issued. for both column and row addresses the first address cycle always contains the least significant address bits and the last address cycle always contains the most significant address bits. if there are bits in the most significant cycl es of the column and row addr esses that are not used then they are required to be cleared to zero . the row address structure is shown in figure 7 with the least significant r ow address bit to the right and the most significant row address bit to the left. msb lsb figure 7. row address layout the page address is set by the least significant row address bits, and the lun address is set by the most significant row address bit(s). the block address is between a page address and a lun address. a host shall not access an address of a page or block beyond maximum page address or block address. the addressing of this device is shown in table 21 . table 21 the addressing of this device. dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 first cycle (column address 1) c1-7 c1-6 c1-5 c1-4 c1-3 c1-2 c1-1 c1-0 second cycle (column address 2) l c2-6 c2-5 c2-4 c2-3 c2-2 c2-1 c2-0 third cycle (row address 1) r1-7 r1-6 r1-5 r1-4 r1-3 r1-2 r1-1 r1-0 fourth cycle (row address 2) r2-7 r2-6 r2-5 r2-4 r2-3 r2-2 r2-1 r2-0 fifth cycle (row address 3) l l l l l r3-2 r3-1 r3-0 r1-0 to r1-7: page address r2-0 to r3-2: block address note : 1) the least significant bit of block address is also regarded as plane address bit. refer to 3.1.1. 2) if the target of the devi ce has only one lun, no lun address bit is assigned. 3.1.1. plane addressing the plane address comprises the lowest orde r bits of the block address as shown in figure 8. msb lsb figure 8. position of plane address lun address block address page address plane address bit(s) lun address block address page address
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 24 3.1.2. extended blocks arrangement the device has 36 extended blocks per plane (extended blocks) to increase valid bl ocks. extended blocks can be accessed by the following addressing. table 22 extended blocks arrangement row address block assignment 000000h block 0( plane 0 ) 000100h block 1( plane 0 ) 000200h block 2( plane 0 ) 000300h block 3( plane 0 ) 000400h block 4( plane 0 ) 000050h block 5( plane 0 ) | | 03fe00h block 1022( plane 0 ) 03ff00h block 1023( plane 0 ) lun #0 main blocks ( 1024 blocks ) 040000h block 1024( plane 0 ) 040100h block 1025( plane 0 ) | | 042200h block 1058( plane 0 ) 042300h block 1059( plane 0 ) lun #0 extended blocks ( 36 blcoks ) 042400h ? ffffffh address gap note : 1) ` ! ???? is only for the device having multiple luns per a target and shall be ignored for the device having single lun per a target.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 25 3.2. factory defect mapping the flash array is not presumed to be pristine, and a number of defects that makes the blocks unusable may be present. invalid blocks shall be sorted out from normal blocks by software. 3.2.1. device requirements if a block is defective, the manufacturer shall mark the bl ock as defective by setting the defective block marking, as shown in figure 9, of the first or last page of the defective block to a value of non-ffh. t he defective block marking is located on the first byte of us er data area or the first byte of spare data area in the pages within a block. figure 9. area marked in first or la st page of block indicating defect ... ... defective block marking 0 ... ... 0 1st page last page 1 2 2 1 the 1st byte of spare region the 1st byte of spare region
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 26 3.2.2. host requirements the host shall not erase or program bl ocks marked as defective by the manufacturer, and any attempt to do so yields indeterminate results. figure 10 outlines the flow chart how to create an initial invalid block table. it should be performed by the host to create the initial bad block table prior to performing any erase or programming operatio ns on the target. all pages in non-defective blocks are read ffh with ecc enabled on the controller. a defective block is indicated by the majority of bits being read non-ffh in the defective block ma rking location of either the first page or last page of the block. the host shall check the defe ctive block marking location of both th e first and last past page of each block to verify the block is valid prior to any er ase or program operations on that block. note : over the lifetime use of a nand device, the defective block marking of defective blocks may encounter read disturbs that cause bit changes. the initial defect marks by the manufacturer may change value over the lifetime of the device, and are expected to be read by the host and us ed to create a bad block tabl e during initial use of the part. figure 10. flow chart to creat e initial invalid block table note : 1) the location for the initial invalid block may vary depending on vendors no yes check ffh 1st byte of (user data or spare data) 1) of the last page a ccessing th e 1st block end pass pass fail start check ffh 1st byte of (user data or spare data) 1) of the first page update bad block table fail last block a ccessing next block
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 27 4. function description 4.1. discovery and initialization toggle ddr1.0 nand is designed to o ffer protection from any in voluntary program/erase during power-transitions. an internal voltage detector disables all functions whenever vcc is below about 2v. the reset command (ffh) must be issued to all ce s as the first command after the nand flash device is powered on. each ce will be busy for 5ms at the maximum after the reset command is issued. du ring busy time of resetting, the acceptable command is the read status (70h). wp pin provides hardware protection and is recommended to be kept at vil during power-up and power-down. the two step command sequence for pro-gram/erase provides additional software protection. figure 11 defines the initiali zation behavior and timings. 4.1.1. single channel discovery host shall set to ?low? the ce which is to enable the target if connected, while all other ce are set to ?high?. host shall then issue the reset command (ffh) to the target. following the re set, the host should then issue the read id command to the target. if the host read out 6 cy cles data by the read id co mmand with address 00h, then the corresponding target is connected. if the id values are not returned or any error is encountered within the sequence, then the corresponding target may not be connect ed properly and no further use of the target shall be done. 4.1.2. dual channel discovery if there are dual channel in a package, host should issues the reset command (ffh) to both channels to initialize all luns. note that the relationsh ips are described between several ce and dual channels. see the table 2 for further inform ation. the sequence of initialization is the sa me as the sequence for single channel discovery. host shall set to ?low? the ce which is to enable the target if connected, while all other ce are set to ?high?. host shall then issue the reset command (ffh) to the target. following th e reset, the host should then issue a read id command to the target. if the host read out 6 cycles data by the read id comma nd with address 00h, then th e corresponding target is connected. if the id values are not returned or any error is encountered within the sequence, then the corresponding target may not be connected properly and no further use of the target shall be done.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 28 figure 11. initialization timing note: 1) during the initialization, the devi ce consumes a maximum current of i cc1 . 100us tcals twp twb 5ms max operation tcas tcah tcs tcalh 1ms min 2.5v 2.5v 2.5v 0.5v 0.5v ff h vcc ce cle ale wp we re dqx r/b 2.7v 2.7v 2.7v 1ms min 3.3v vccq : 2.5v 1.8v vccq : 1.5v 0.5v 0.5v vccq 3.3v vccq : 2.7v 1.8v vccq : 1.7v 3.3v vccq : 2.5v 1.8v vccq : 1.5v 3.3v vccq : 2.7v 1.8v vccq : 1.7v 3.3v vccq : 2.5v 1.8v vccq : 1.5v 1.8v vccq : 1.7v 3.3v vccq : 2.7v
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 29 4.2. mode selection after initialization, the sdr in terface is active for all targets on the devi ce. each target's interface is independent of other targets, so the host is resp onsible for changing the interface for each target. the interface can be changed by set feature command defined in section 5.2.8. table 23 describes the bus state for the toggle ddr1.0. command, address and data are all written through dq's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable (cle) and address latch enable (ale) are used to multiplex command and address respectively, via the dq pins. host reads or writes data to the device using dqs signal . and data are latched on both falling and rising edges of dqs on data input. table 23 toggle ddr1.0 interface mode selection cle ale ce we re dqs wp command input h l l h x (1) x address input l h l h x x command input h l l h x h address input l h l h x h data input l l l h h h data output l l l h x during read(busy) x x x x h x x during program(busy) x x x x x x h during erase(busy) x x x x x x h write protect x x x x x x l stand-by x x h x x x 0v/vcc (2) note: 1) x can be vil or vih. 2) wp should be biased to cmos high or cmos low for standby. table 24 describes the bus state for the sd r interface. command, address and data are all written through dq's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable (cle) and address latch enable (ale) are used to multiplex command and address respectively, via the dq pins. host reads the data to the device using re signal and writes the data to the device using we signal. table 24 sdr interface mode selection cle ale ce we re wp * 1 command input h l l h * data input l l l h h address input l h l h * serial data output l l l h * during program (busy) * * * * * h during erase (busy) * * * * * h * * h * * * during read (busy) * * l h ( * 2) h ( *2) * program, erase inhibit * * * * * l stand-by * * h * * 0 v/v cc note: h: v ih , l: v il , * : v ih or v il * 1: refer to application note (10) toward the end of this document regarding the wp signal when program or erase inhibit * 2: if ce is low during read busy, we and re must be held high to avoid unintended command/address input to the device or read to device. reset or status read command can be input during read busy.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 30 4.2.1. toggle ddr1.0 general timing 4.2.1.1. command latch cycle figure 12. command latch cycle timing note : 1) command information is latched by we going ?high?, when ce is ?low?, cle is ?high?, and ale is ?low?. 2) dqs shall be set to low when these comma nds (85h, 10h, 11h, or 15h) are input. 4.2.1.2. address latch cycle figure 13. address latch cycle timing note : 1) address information is latched by we going ?high?, when ce is ?low?, cle is ?low?, and ale is ?high?. re ce cle t wp we t cas dqs ale dq[7:0] t cah t cals t calh t cals t calh t cs t ch command high high high high re ce cle t wp we t cas dqs ale dq[7:0] t cah t cals t calh t cals t calh t cs address t ch high high high high : don?t care
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 31 4.2.1.3. basic data input timing figure 14. basic data input timing note: 1) dqs, and data input buffers are turned-on when ce and dqs goes ?low? and data inputs begin with dqs, toggling simultaneously. 2) ale and cle should not toggle during t wpre period regardless of t cals . 3) dqs and data input buffers ar e turned-off if either cle or ce goes ?high?. 4) the least significant bit of the column address shall always be zero. 5) dqs, shall be either high or low before data-input condition is set. : don?t care : don?t care ce dq[7:0] dqs t cals t ds t wpre t d q sh t d q sl t dsc t wpst t wpsth cle ale t d q sl t d q sh t dsc t dh t ds t dh d0 d1 d2 d3 d n-2 d n-1 d n t ds t dh t ds t dh we high t cals high re bus idle bus idle data input t cs
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 32 4.2.1.4. basic data output timing figure 15. basic data output timing note: 1) dqs, and dq driver s are turned-on when ce and re goes low for data out operation. 2) ale and cle should not toggle during t rpre period regardless of t cals . 3) dqs and dq drivers turn from valid to high-z if either cle or ce goes high. 4) the least significant bit of the column address shall always be zero. ce t cr dq[7:0] t d q sre dqs t rc t chz t d q sre t d q s q t dqsq t q hs t q hs t q h t d q s q t q hs hi-z hi-z t dqsre t dvw hi-z re hi-z t rpre t reh t rp t reh t rp t rc t rpst t rpsth cle low ale low high we t d q sre bus idle data output bus idle d0 d1 d2 dn-3 dn-2 dn-1 dn : undefined ( driven b y nand )
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 33 4.2.1.5. read id operation figure 16. read id operation timing note: 1) even though toggle-mode nand us es both low- and high-going edges of dqs for reads, read id operation repeats each data byte twice, so that read id ti ming becomes identical to that conventional nand 2) dqs and dq drivers turn from valid to high-z when ce or cle goes high. 3) address 00h is for toshiba conventional nand and 40h is for new jedec id information. ce cle we t d q sre d q s ale dqx t chz t cals t cs re 2nd id t rpre t ar t whr (3) hi-z hi-z hi-z t cals t cals t cals 1st id 00h/40h 90h nth id : don?t care : undefined(driven by nand)
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 34 4.2.1.6. status read cycle figure 17. status read cycle timing note: 1) even though toggle-mode nand uses both low- and hi gh-going edges of dqs for reads, status read operation repeats same output until device status changes 2) dqs and data out buffers turn from valid value to high-z when ce or cle goes high. 3) re can toggle more than once. 4) read status enhanced command (78h) requires row address setting steps before reading status value although it is omitted in the above figure. ce cle we t d q sre dqs ale dqx t chz t cs re t rpre t wp (3) hi-z hi-z hi-z t cals t calh status out t whr (3) t chz t cas t cah 70h/78h/f1h t dqsq : don?t care : undefined(driven by nand)
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 35 4.2.1.7. set feature figure 18. set feature timing 4.2.1.8. get feature figure 19. get feature timing ce cle we dqs ale dqx re t wpre t cd q ss t cals efh xxh w-b0 w-b1 w-b2 w-b3 t wb t feat r/ b : don?t care ce cle we d q s ale dqx re t d q sre eeh xxh r-b0 r-b1 r-b2 r-b3 t wb t feat t rr r/ b : don?t care : undefined(driven by nand)
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 36 4.2.1.9. page read operation figure 20. page read operation timing read hold operation with ce high is below figure 21. read hold operation with ce high : undefined : don?t care ce cle we dqs ale dqx re t wc t dqsre t rr r/ b t wb hi-z t rpre t rc t rpsth t rpst hi-z hi-z hi-z t r column address add add add add add 30h row address 00h t cr t cr 1 : undefined : don?t care ce cle we dqs ale dqx re r/ b t rpsth t rpst 1 t cres t cr t rpre hi-z hi-z
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 37 4.2.1.10. page program operation figure 22. page program operation timing note: 1) read status enhanced command (78h) requires row address setting steps before reading status value although it is omitted in the above figure. hi-z ce cle we dqs ale dqx re t cd q ss t prog r/ b t cals t wpre t wpst dq0 column address add add add add add t wpsth t cd q sh 10h d0 d1 dn 80h row address 70h/78h/f1h dq0=0 successful program dq0=1 error in program t adl : don?t care
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 38 4.2.2. sdr general timing 4.2.2.1. command latch cycle figure 23. command latch cycle timing 4.2.2.2. address latch cycle figure 24. address latch cycle timing t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il ce cle we ale dq[7:0] add add add : v ih or v il t dh t ds t cls cle t als t alh t wp t wh t wp add t dh t ds t cs t cs we ale dq[7:0] t dh t ds t wp t wh t dh t ds t wp t wh t wc t dh t ds t wp t wh t wc add t clh t ch t ch column address row address ce
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 39 4.2.2.3. basic data input timing figure 25. basic data input timing 4.2.2.4. basic data output timing figure 26. basic data output timing command dq[7:0] t rc t dh t rp t rp we cle ce ale re t rloh t reh t rea t rhz t rea t cs2 t cls2 t clh t ch t rp t rr t rea t rloh t ds by/ry t chz t rhoh t rhoh dout dout t alh t cr t clhz we t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle ce dq[7:0] d in n t dh t ds t dh t ds t cs t cls t ch t cs t alh
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 40 4.2.2.5. read id operation figure 27. read id operation timing 4.2.2.6. status read cycle figure 28. status read cycle timing : v ih or v il * : 70h represents the hexadecimal number t whr we t dh t ds t cls t clr t cs t clh t ch t wp status output 70h * t whc t ir t rea t rhz t chz ce cle re by/ry dq[7:0] t rhoh t cea t cr : v ih or v il we cle re t cr ce ale dq[7:0] t ar id read command address 00 maker code t rea t cls t cs t ds t ch t alh t als t cls t cs t ch t alh t dh 90h 00h 1 st id t rea t rea t rea 3 rd id t rea 5 th id 2 nd id t rea 6 th id t whr1 4 th id
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 41 4.2.2.7. set feature figure 29. set feature timing 4.2.2.8. get feature figure 30. get feature timing ce cle we ale dq[7:0] re efh 10h w-b0 w-b1 w-b2 w-b3 t wb t feat by/ry t wc t wp t wh t ds t dh t cs t adl : v ih or v il : do not input data while data is being output. ce cle we ale dq[7:0] re eeh 10h r-b0 r-b1 r-b2 r-b3 t wb t feat t rr by/ry t chz t rhz t re a t rp t reh t rc
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 42 4.2.2.9. page read operation figure 31. page read operation timing 30h add add add add add dq[7:0] t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t clr t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea column address data out from col. add. n t dh t ds 00h d out n d out n ? 1 by/ry t cea row address
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 43 4.2.2.10. page program operation figure 32. page program operation timing add t cls t cls t als t ds t dh we cle ce ale re by/ry : v ih or v il t clh t ch t cs t ds t dh t alh dq[7:0] : do not input data while data is being output. t cs t dh t ds t dh t prog t wb t ds t alh t als add d in n d in m 10h 70h status output add add add 80h d in n+1 t adl column address row address * ) m: up to 17664 (byte input data for ? 8 device).
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 44 4.3. ac timing characteristics 4.3.1. t iming parameters description table 25 timing parameters description toggle ddr1.0 parameter description t r data transfer from flash array to register t prog program time t berase erase time t adl address to data loading time t ar ale low to re low t calh cle/ale hold time t cals cle/ale setup time t cah command/address hold time t cas command/address setup time t ch ce hold time t cdqsh dqs hold time for data input mode finish t cdqss dqs setup time for data input mode start t chz ce high to output hi-z t clhz cle high to output hi-z t clr cle to re low t coh data hold time after ce disable t cr ce low to re low t cres re setup time before ce low t cs ce setup time t cwaw command write cycle to address write cycle time for random data input t dh data hold time t dqsh dqs input high pulse width t dqsl dqs input low pulse width t dqsq output skew among data output and corresponding dqs t dqsre re to dqs and dq delay t dsc data strobe cycle time t ds data setup time t dvw output data valid window t feat busy time for set feature and get feature t qh output hold time from dqs t qhs dqs hold skew factor t rc read cycle time t reh re high pulse width t rp re low pulse width t rpp re low pulse width for read status at power-up sequence t rpre read preamble t rpst read postamble t rpsth read postamble hold time t rr ready to re high t rst device resetting time(read/program/erase) t wb we high to busy t wc write cycle time t wh we high pulse width t whr we high to re low t whr2 we high to re low for random data out t wp we low pulse width
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 45 t wpre write preamble t wpst write postamble t wpsth write postamble hold time t ww wp high/low to we e low t dcbsyw1 data cache busy time in write cache (following 11h) t dcbsyw2 data cache busy time in write cache (following 15h) t dcbsyr cache busy in read cache t dcbsyr2 dummy busy time for page copy(2) read sdr parameter description t cls cle setup time t cls2 cle setup time t clh cle hold time t cs ce setup time t cs2 ce setup time t ch ce hold time t wp we low pulse width t als ale setup time t alh ale hold time t ds data setup time t dh data hold time t wc write cycle time t wh we high pulse width t adl* address to data loading time t ww wp high to we low t rr ready to re falling edge t rw ready to we falling edge t rp re low pulse width t rc read cycle time t rea re access time t cr ce low to re low t clr cle low to re low t ar ale low to re low t rhoh data output hold time from re high t rloh data output hold time from re low t rhz re high to output high impedance t chz ce high to output hi-z t clhz cle high to output hi-z t reh re high pulse width t ir output-high-impedance-to- re falling edge t rhw re high to we low t whc we high to ce low t whr1 we high to re low (status read) t whr2 we high to re low for random data out t wb we high to busy t rst device resetting time(read/program/erase) t cea ce access time t feat busy time for set feature and get feature
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 46 4.3.2. timing parameters table table 26 ac timing charateristics toggle ddr1.0 100mhz parameter symbol min max unit address to data loading time t adl 300 - ns ale low to /re low t ar 10 - ns cle/ale hold time t calh 5 - ns cle/ale setup time t cals 15 - ns command/address hold time t cah 5 - ns command/address setup time t cas 5 - ns dqs hold time for data input mode finish t cdqsh 100 - ns dqs setup time for data input mode start t cdqss 100 - ns /ce hold time t ch 5 - ns /ce high to output hi-z t chz - 30 ns cle high to output hi-z t clhz - 30 ns cle to re low t clr 10 - ns data hold time after ce disable t coh 5 - ns /ce low to /re low t cr 10 - ns /re setup time before /ce low t cres 10 - ns /ce setup time t cs 20 - ns command write cycle to address write cycle time for random data input t cwaw 300 - ns data hold time t dh 0.9 - ns dqs input high pulse width t dqsh 0.4*t rc - ns dqs input low pulse width t dqsl 0.4*t rc - ns output skew among data output and corresponding dqs t dqsq - 0.8 ns /re to dqs and dq delay t dqsre - 25 ns data strobe cycle time t dsc 10 - ns data setup time t ds 0.9 - ns output data valid window t dvw t dvw = t qh - t dqsq ns busy time for set feature and get feature t feat - 1 ? s output hold time from dqs t qh t qh = min[t reh , t rp ] - t qhs ns dqs hold skew factor t qhs - 0.8 ns /re read cycle time t rc 10 - ns /re high pulse width t reh 0.4*t rc - ns /re low pulse width t rp 0.4*t rc - ns re low pulse width for read status at power-up sequence t rpp 30 - ns read preamble t rpre 15 - ns read postamble t rpst t dqsre + 0.5xtrc - ns read postamble hold time t rpsth 25 - ns ready to /re high t rr 20 - ns device resetting time (read/program/erase) t rst (1) 10 /30 /100 ? s /we high to busy t wb - 100 ns write cycle time t wc 25 - ns /we high pulse width t wh 11 - ns /we high to low t whr 120 - ns /we high to /re low for random data out t whr2 300 - ns
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 47 /we low pulse width t wp 11 - ns write preamble t wpre 15 - ns write postamble t wpst 6.5 - ns write postamble hold time t wpsth 25 - ns /wp high/low to /we low t ww 100 - ns sdr parameter symbol min max unit cle setup time t cls 10 ? ns ? cle setup time t cls2 40 ?? ns ? cle hold time t clh 5 ? ns ? ce setup time t cs 15 ? ns ? ce setup time t cs2 32 ?? ns ? ce hold time t ch 5 ? ns ? write pulse width t wp 10 ? ns ? ale setup time t als 10 ? ns ? ale hold time t alh 5 ? ns ? data setup time t ds 5 ? ns ? data hold time t dh 5 ? ns ? write cycle time t wc 20 ? ns ? we high hold time t wh 7 ? ns ? address to data loading time t adl* 300 ?? ns ? wp high to we low t ww 100 ? ns ? ready to re falling edge t rr 20 ? ns ? ready to we falling edge t rw 20 ?? ns read pulse width t rp 10 ?? ns ? read cycle time t rc 20 ? ns ? re access time t rea ? 16 ns ce low to re low t cr 9 ? ns ? cle low to re low t clr 10 ? ns ? ale low to re low t ar 10 ? ns ? data output hold time from re high t rhoh 25 ? ns ? data output hold time from re low t rloh 5 ?? ns ? re high to output high impedance t rhz ?? 60 ns ce high to output high impedance t chz ? 30 ns cle high to output high impedance t clhz ? 30 ? ns re high hold time t reh 7 ? ns ? output-high-impedance-to- re falling edge t ir 0 ? ns ? re high to we low t whr 30 ?? ns we high to ce low t whc 30 ? ns ? we high to re low (status read) t whr1 180 ? ns ? we high to re low (column address change in read) t whr2 300 ? ns ? we high to busy t wb ? 100 ns device reset time (ready/read/program/erase) t rst ? 10/30/100 ? s ce access time t cea ?? 25 ? ns busy time for set feature and get feature t feat ?? 1 ? s note : the values in this table are preliminary and subject to change.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 48 table 27 ac test conditions toggle ddr1.0 parameter condition input pulse levels vil to vih input rise and fall times 1.0v/ns input and output timing levels vccq/2 output load 50 ohms to vtt (vtt=0.5*vccq) sdr (vccq=3.3v) parameter condition input pulse levels 0 v to v cc input rise and fall times 3ns input comparison level v cc /2 output data comparison level v cc /2 output load c l (50 pf) ? 1 ttl sdr (vccq=1.8v) parameter condition input pulse levels 0 v to v cc input rise and fall times 3ns input comparison level v cc /2 output data comparison level v cc /2 output load c l (30 pf) ? 1 ttl note : 1) busy to ready time depends on the pull-up resistor tied to the by/ry pin. (refer to application note (9) toward the end of this document.) table 28 read/program/erase timing characteristics description parameter typ. max. unit data transfer from cell to register t r 50 (tentative) 100 (tentative) ? s average programming time t prog 1400 (tentative) 3000 (tentative) ? s block erasing time t berase 5 (tentative) 10 (tentative) ms data cache busy time in write cache (following 11h or 32h) t dcbsyw1 0.5 1 ? s data cache busy time in write cache (following 15h) t dcbsyw2 - 3000 (tentative) ? s cache busy in read cache t dcbsyr - 100(tentative) ? s dummy busy time for page copy(2) read t dcbsyr2 - 105(tentative) ? s number of partial program cycles in the same page - - - cycle ? note : 1)t prog is the internal program time from a ca che or page register to nand array. t r is the internal loading time from nand array to the a cache or page register. 2) t dcbsyw2 depends on the timing between internal programming time and data in time. 3) tprog and tdcbsyw2 are the average busy time in a block. the absolute maximum for one page operation is 5000 ? s .
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 49 5. command description and device operation 5.1. basic command sets toggle ddr1.0 nand flash memory has addresses multip lexed into 8 i/os. command, address and data are all written through dq [7:0] by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable (cle) and address latch enable (ale) are used to multiplex command and address respectively, via the dq[7:0] pins. commands which apply to a specific page or block typically have a second command and ones that apply to a target or a lun have a first command only. table 29 below defines the basic command sets. table 29 basic command sets function primary or secondary 1st set address cycles 2nd set acceptable while accessed lun is busy acceptable while other luns are busy page read primary 00h 5 30h y sequential cache read primary 31h - - y read start for last page cache read primary 3fh - - y random cache read primary 00h 5 31h y page program primary 80h 5 10h y cache program primary 80h 5 15h y block erase primary 60h 3 d0h y read for copy-back primary 00h 5 35h y copy-back program primary 85h 5 10h y random data input (1) primary 85h 2 - y random data output (1) primary 05h 2 e0h y set feature primary efh 1 - get feature primary eeh 1 - read id primary 90h 1 - y read status primary 70h - - y y read status2 primary 71h - - y y reset primary ffh - - y y reset lun - fah 3 - y y note: 1) random data input/output can be executed in a page. caution: any undefined command inputs are prohibit ed except for above command set.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 50 5.2. basic operation 5.2.1. page read operation the page read function reads a page of data identified by row address for the selected lun. the page of data is made available to be read from the page register starting at the specified column address. figure 33 defines the pag e read behavior and timings. reading beyond the end of a page results in indeterm inate values being returned to the host. figure 33. page read timing 5.2.1.1. page read operation with random data output the random data output function change s the column address from which data is being read in the page register for the selected lun. the random data output command sh all only be issued when th e lun is in a read idle condition. figure 34 defines the random data output behavior an d timin gs. the host shall not read data from the lun until t whr2 (ns) after the second(i.e. e0h) is written to the lun. figure 34. page read with random data output timing dq[7:0] 0 0h r/ b t wb t r c1 c2 r1 r2 r3 30h r-data(serial access) t rr data field spare field t rr t wb dq[7:0] r/ b t r c1 c2 r1 r2 r3 30h r-data high t whr2 dq[7:0] r/ b c1 c2 e0h r-data 05h 00h 1 1
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 51 5.2.1.2. data out after status read while monitoring the read stat us to determine when the t r (transfer from flash array to a page register) is complete, the host shall re-issue the 00h command to star t reading data. issuing the 00h command will cause data to be returned starting at the selected column address. figure 35. data out after status read timing 5.2.2. sequential cache read operation the sequential cache read operation permits a page to be read from the page register while another page is simultaneously read from the flash arra y for the selected lun. a read page command shall be issued prior to the initial sequential cache read command in a cache read sequence. a sequential cache read command shall be issued prior to the read start for last page cache read command (3fh) being issued. the sequential cache read command may be issued after the read function is complete (i.e. sr[6] is set to one). data output always begins at column address 00h. when the sequential cache read command (i.e. 31h) is issued, sr[6] is cleared to zero (i.e. busy). after the operation finishes, sr[6] turns to one (i.e. ready) and the host may begin to read the data loaded by the previous sequential cache read operation. the data loaded by a sequential cache read command from flash array to a page register is copied to a cache register by a following sequential cache read command. and the data of a final page loaded onto a page register is transferred to a cache register by 3fh command. the host shall not issue a sequential cache read command (31h) after the last page of a block is read. figure 36 defines the sequential cache read behavior and timings. fig ure 36. sequential cache read timing dq[7:0] r/ b t 3fh r-data t dcbsyr t rr 1 r-data t wb 31h r-data t dcbsyr t rr dq[7:0] 0 0h r/ b t wb t r c1 c2 r1 r2 r3 30h t whr 70h sr [ 0 ] 00h r-data t whr2 dq[7:0] 0 0h r/ b t wb t r c1 c2 r1 r2 r3 30h t wb 31h 31h r-data t dcbsyr t rr t dcbsyr t wb 1
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 52 5.2.3. random cache read operation a read page command shall be issued prior to the initial random cache read command in a cache read sequence like the sequential cache read operatio n. a random cache read command shall be issued prior to the read start for last page cache read command (3fh) being issued. th e page and block address can be accessed in a random manner. data output always begins at column address 00h. figure 37 defines the random cache read behavior and timing s. figure 37. random cache read timing 5.2.4. page program operation the device is programmed basically on a page basis, and each page shall be programmed only once before being erased. the addressing order shall be se quential within a block. the contents of the page register are programmed into the flash array specified by row a ddress. sr[0] is valid for this command after sr[6] transitions from zero to one until the next transition of sr[6] to zero. figure 38 defines the page progra m behavior and timings. writing beyond the end of the page register is undefined. figure 38. page program timing 5.2.4.1. program operation with random data input the device supports random data input in a page. the column address for the next data, which will be written, may be changed to the address using random data input co mmand (i.e. 85h). random data input may be operated multiple times without limitation. figure 39. program operation with random data input timing dq[7:0] 0 0h r/ b t wb t r c1 c2 r1 r2 r3 30h 31h r-data t rr 1 t wb dq[7:0] r/ b t wb 3fh r-data t dcbsyr t rr 1 t wb 31h r-data t dcbsyr t rr 0 0h c1 c2 r1 r2 r3 0 0h c1 c2 r1 r2 r3 t dcbsyr dq[7:0] r/ b w-data 80h c1 c2 r1 r2 r3 t wb 10h t whr 70h sr [ 0 ] t adl t prog dq[7:0] r/ b w-data 80h c1 c2 r1 r2 r3 t wb 10h t whr 70h sr [ 0 ] t adl t prog 85h c1 c2 w-data t adl t cwaw
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 53 5.2.5. cache program operation the cache program function allows the ho st to write the next data for another page to the page register while a page of data to be programmed to the flash array fo r the selected lun. when command 15h is issued, r/ b returns high (i.e. ready) when a cache register is ready to be written after data in the cache register is transferred to a page register. however, when command 10h is issued for the final page, r/ b turns to high after outstanding program operation performed by previo us cache program command and the prog ram operation for the final page is completed. sr[0] is valid for this command after sr[5] tran sitions from zero to one unt il the next transition. sr[1] is valid for this command after sr[6] transitions from zero to one, and it is invalid after the first cache program command completion since there is no previous cache program operation. cache pr ogram operation shall work only within a block. figure 40 defines the cache program behavior and timings. note that t prog at the end of the caching operation may be longer than ty pical as this time also includes completing the programming operation for the previous page. writing beyond the end of the page register is undefined. figure 40. cache program timing 5.2.6. block erase operation the block erase operation is done on a block basis. only three cycles of row addresses are required for block erase operation and a page address within th e cycles is ignored while plane and block address are valid. after block erase operation passes, all bits in the block shall be set to one. sr[0] is valid for this command after sr[6] transitions from zero to one( i.e. the selected lun is ready) until the lun goes in busy state by a next command. figure 41 defines the block erase behavior and timings. fig ure 41. block erase timing dq[7:0] r/ b w-data 80h c1 c2 r1 r2 r3 t wb 15h t adl t dcbsyw2 w-data t adl t wb 10h t whr 70h sr [ 0 ] t prog w-data dq[7:0] r/ b 80h c1 c2 r1 r2 r3 1 max. number of pages in a block-1 repeatable last page program last page program 1 t wb d0h t whr 70h sr [ 0 ] t berase dq[7:0] r/ b 60h r1 r2 r3
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 54 5.2.7. copy-back program operation the copy-back program with read for copy-back is configured to efficiently rewrite data stored in a page of a block to a page of the other block without data re-loadi ng when no error within the page is found. since the time-consuming re-loading cycles are removed, copy-bac k operation helps the system performance improve. the benefit is especially obvious when a part of a block is updated and the rest of th e block also needs to be copied to the newly assigned free block. the copy-back operation consists of ?read for co py-back? and ?copy-back program?. a host reads a page of data from a source page using ?read for copy-back? and copies read data back to a destination page on the same lun by ?copy-back program? command . copy-back program operation shall work only within the same plane. figure 42 defines the copy-back program behavior and timings. not e: the least significant bit of page address shall be the same between source and destination pages. in other words, the page of even page address cannot be copied to the page of odd page address, and the page of odd page address cannot be copied to the page of even page address as well. figure 42. copy-back program timing 5.2.7.1. copy-back program operation with random data input after a host completes to read data from a page regist er, the host may modify data using random data input command if required. figure 43 defines the copy-back program with random data input behavior and timings. fig ure 43. copy-back program with random data input timing dq[7:0] r/ b 00h c1 c2 r1 r2 r3 w-data t adl t wb 10h t whr 70h sr [ 0 ] t prog w-data dq[7:0] r/ b 85h c1 c2 r1 r2 r3 1 1 35h r-data t rr t wb t r dq[7:0] r/ b 00h c1 c2 r1 r2 r3 t wb 10h t whr 70h sr [ 0 ] t prog w-data dq[7:0] r/ b 85h c1 c2 r1 r2 r3 1 1 35h r-data t rr t wb t r 85h c1 c2 t adl
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 55 5.2.8. set feature operation users may set particular features using ?set feature? operation. figure 44 defines the set features behavior and timing s and table 30 defines features that users can change. once set feature operation begins, the operation shall be completed without any disturbance and interruption such as reset operation. figure 44. set feature timing note: the feature-setting shall work on lower than 133mbps. table 30 set feature addresses 1 st cycle 2 nd cycle description 10h driver strength setting efh 80h interface change efh t adl dq[7:0] w-b0 w-b1 w-b2 w-b3 xxh r/ b t feat t wb
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 56 hi-z hi-z 5.2.8.1. driver strength setting (10h) driver strength is configured according to the b0 value. table 31 driver strength setting data b0 value description 00h ~ 01h reserved 02h driver multiplier : underdrive 03h reserved 04h driver multiplier : 1 (default) 05h reserved 06h driver multiplier : overdrive 1 07h reserved 08h reserved 09h ~ ffh reserved note: b1, b2 and b3 are reserved and shall be written with 00h. table 32 interface change setting data b0 value dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 description 0 0 0 0 0 0 0 0 to toggle ddr1.0 0 0 0 0 0 0 0 1 to sdr 5.2.9. get feature operation users find how the target is set through ?get feature? command. the function shall return the current setting information. if a host starts to read the first byte of da ta (i.e. b0 value), the host shall complete reading all four bytes of data before issuing another command (inc luding read status or read status enhanced). figure 45 defines the get featur es behavior and timings. if read status (or read status enhanced) is used to monitor whether the t feat time is complete, the host shall issue read command (i.e. 00h) to read b0-b1-b2-b3. figure 45. get feature timing note: the feature-getting shall work on lower than 133mbps. eeh t wb dq[7:0] r-b0 r-b1 r-b2 r-b3 xxh r/ b t feat t rr
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 57 5.2.10. read id operation the id of a target is read by command 90h followed by 00h or 40h address. figure 46 defines read id operation beh avior and timings. figure 46. read id timing 5.2.10.1. 00h address id definition users can read six bytes of id containing manufacturer code, device code and architecture information of the target by command 90h followed by 00h address. the command re gister remains in read id mode until another command is issued. table 33 00h address id definition table cycle description tc58teg6d2h 1 st data maker code 98h 2 nd data device code d7h 3 rd data number of lun per target, cell type, etc. 84h 4 th data page size, block size,etc. 93h 5 th data plane number,etc. 72h 6 th data technology code 57h table 34 2nd id data description dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 hex data 8 gbits 1 1 0 1 0 0 1 1 d3h 16 gbits 1 1 0 1 0 1 0 1 d5h 32 gbits 1 1 0 1 0 1 1 1 d7h 64 gbits 1 1 0 1 1 1 1 0 deh 128 gbits 0 0 1 1 1 0 1 0 3ah memory density per target 256 gbits 0 0 1 1 1 1 0 0 3ch table 35 3rd id data description dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 1 0 0 2 0 1 4 1 0 number of lun per target 8 1 1 2 level cell 0 0 4 level cell 0 1 8 level cell 1 0 cell type 16 level cell 1 1 table 36 4th id data description dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 2kb 0 0 4kb 0 1 8kb 1 0 page size (w/o redundant area) 16kb 1 1 128kb 0 0 0 256kb 0 0 1 512kb 0 1 0 1mb 0 1 1 2mb 1 0 0 4mb 1 0 1 block size (w/o redundant area) reserved 1 x x *x : either 0 or 1 90h t whr r-1stc yc r-2ndc yc r-3rdc yc r-4thc yc r-5thc yc r-6thc yc 00h/40h
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 58 table 37 5th id data description dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 1 0 0 2 0 1 4 1 0 number of plane per target 8 1 1 table 38 6th id data description dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 130 nm process 0 0 0 90 nm process 0 0 1 70 nm process 0 1 0 56 nm process 0 1 1 43 nm process 1 0 0 32 nm process 1 0 1 24 nm process 1 1 0 technology code 19 nm process 1 1 1 conventional 0 interface toggle ddr1.0 mode 1 note: as for table 38 ?6th id data?, even if the interface is changed into t oggle ddr1.0 b y setfeature, the value of "interface" is still 0. 5.2.10.2. 40h address id definition toggle ddr1.0 nand also provides six bytes of jedec stan dard signature id. users can read the id by command 90h followed by 40h address. any data returned after th e six bytes of jedec standard signature is considered reserved for future use. table 39 40h address id cycle 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle 4ah 45h 44h 45h 43h 01h table 40 40h address id definition cycle description dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 1st j 0 1 0 0 1 0 1 0 2nd e 0 1 0 0 0 1 0 1 3rd d 0 1 0 0 0 1 0 0 4th e 0 1 0 0 0 1 0 1 5th c 0 1 0 0 0 0 1 1 6th conventional asynchronous sdr toggle ddr1.0 synchronous ddr 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 59 5.2.11. read status operation in the case of non-multi-plane operat ions, the 70h read status function retrieves a status value for the last operation issued. if multi-plane operat ions are in progress on a single lun, then 70h read status returns the composite status value. specifically, 70h read status sh all return the combined stat us value of the independent status register bits according to table 41 . on the other hands, 71h read status returns statuses of two planes on a single lun according to table 42 . figure 47 defines the read status behavior and timings. table 41 read status definition for 70h dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 definition of value pass : "0" fail : "1" pass : "0" fail : "1" reserved reserved reserved busy : "0" ready : "1" busy : "0" ready : "1" protected : "0" not protected : "1" block erase pass/fail not use not use not use not use not use busy/ready write protect page program pass/fail not use not use not use not use not use busy/ready write protect cache program pass/fail for the current page pass/fail for the previous page not use not use not use busy/ready for flash array busy/ready for host write protect read not use not use not use not use not use not use busy/ready write protect cache read not use not use not use not use not use busy/ready for flash array busy/ready for host write protect copy-back pass/fail not use not use not use not use not use busy/ready write protect note: 1) during block erase, page program or copy-back operation, dq 0 is on ly valid when dq6 shows the ready state. 2) during cache program operation, dq 0 is only valid when dq 5 shows the ready state, and dq 1 is only valid when dq 6 shows the ready state. table 42 read status definition for 71h dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 definition of value pass : "0" fail : "1" pass : "0" fail : "1" pass : "0" fail : "1" pass : "0" fail : "1" pass : "0" fail : "1" busy : "0" ready : "1" busy : "0" ready : "1" protected : "0" not protected : "1" block erase pass/fail pass/fail for plane#0 pass/fail for plane#1 not use not use not use busy/ready write protect page program pass/fail pass/fail for plane#0 pass/fail for plane#1 not use not use not use busy/ready write protect cache program pass/fail pass/fail for plane#0 (n) pass/fail for plane#1 (n) pass/fail for plane#0 (n-1) pass/fail for plane#1 (n-1) busy/ready for flash array busy/ready for host write protect read not use not use not use not use not use not use busy/ready write protect cache read not use not use not use not use not use busy/ready for flash array busy/ready for host write protect copy-back pass/fail pass/fail for plane#0 pass/fail for plane#1 not use not use not use busy/ready write protect note: 1) during block erase, page program or copy-back operation, dq 0, dq 1 and dq 2 are only valid when dq6 shows the ready state. 2) during cache program operation, dq 0, dq 1 and dq 2 ar e only valid when dq 5 sh ows the ready state, and dq 3 and dq 4 are only valid when dq 6 shows the ready state. figure 47. read status timing sr[x] 70h / 71h t whr dq[7:0]
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 60 5.2.12. reset operation toggle ddr1.0 nand offers a reset function by command ffh. when the device is in ?busy? state during any operation, the reset operation will abort these operations. the contents of memory cells being programmed are no longer valid, as the data will be part ially programmed or erased. reset during the operation with a cache register (e.g. cache program operation) may not ju st stop the most recent page operatio n but it may also stop the previous page operation depending on when the ff reset is input. although the device is al ready in process of reset operation, a new reset command will be accepted. figure 48 defines the reset behavior and timings. figure 48. reset timing when reset (ffh) command is input during program operation figure 49. reset timing during program operation when reset (ffh) command is input during erase operation figure 50. reset timing during erase operation when reset (ffh) command is input during read operation figure 51. reset timing during read operation 00 ff 00 by/ry t rst for read 30 internal erase voltagt rst d0 ff 00 by/ry t rst for erase internal v pp 80 10 ff 00 by/ry t rst for program ffh t wb dq[7:0] r/ b t rst
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 61 when read status command (70h) is input after reset operation figure 52. status read after reset operation when two or more reset commands are input in succession figure 53. successive reset operation 10 by/ry ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff status : pass/fail ? pass : ready/busy ? ready ff 70 by/ry
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 62 5.2.13. reset lun operation a certain lun within a target can be reset by command fah followed by row addresses. row addresses are required to set a lun to be reset. figure 54 defines the reset lun behavior and timings. figure 54. single lun reset timing note : if there are multiple luns on a target, r/ b is also affected by the rest of lun(s) on the same target . 5.3. extended operation 5.3.1. extended command sets table 43 defines the extended command sets. primary and secondary commands are also categorized in the table. primary commands are recommended to use when a part icular function is impl emented, while secondary commands are for alternative implementation for backward compatibility. table 43 extended command sets function primary or secondary 1st set address cycles for 1st set 2nd set address cycles for 2nd set page copy (2) read primary 00h-- 5 --3ah - page copy (2) program primary 8ch-- 5 --15h - page copy (2) program for last page primary 8ch-- 5 --10h - device identification table read primary ech-- 1 - - read status enhanced primary 78h-- 3 - - read lun#0 status secondary f1h - - - r1 r2 r3 f a h t wb dq[7:0] r/ b t rst row add. 1,2,3
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 63 5.3.2. page copy (2) operation by using page copy (2), data in a page of a block can be copied to a page of the other block after the data has been read out. this operation needs to be ex ecuted within a plane. if the block address is changed, this sequence shall be started from the beginning. data input is required only if previo us data output needs to be changed. if the data needs to be changed, locate the de sired address with the column and ro w address input after 8ch command, and change only the data that n eeds to be changed. make sure wp is held to high level when page copy (2) operation is performed. figure 55 defines page copy (2) behavior and timings. not e: the least significant bit of page address shall be the same between source and destination pages. in other words, the page of even page address cannot be copied to the page of odd page address, and the page of odd page address cannot be copied to the page of even page address as well. figure 55. example timing with page copy (2) dq[7:0] r/ b 00h t wb 30h t r repeatable dq[7:0] r/ b 00h dq[7:0] r/ b w-data 8ch t wb 10h t adl t prog 1 2 1 2 t wb 3ah t dcbsyw2 8ch t wb 15h t dcbsyr2 r-data c1 c2 r1 r2 r3 c1 c2 r1 r2 r3 c1 c2 r1 r2 c1 c2 r1 r2 r3 w-data t adl r3 r-data
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 64 5.3.3. device identificati on table read operation the device returns a jedec standard formatted para meter page during the da ta out phase of the read parameter page command when address 40h is in putted. the read parameter page command is a ech value for the command cycle and a 40h value for the addr ess cycle, and the bytes of the parameter page are returned in the data output (dout) cycles. after the command ech address 40h is received by the nand device, it will go busy for a period of time (t r in the figure) after which, the parameter page can be read from the device. the length and contents of the parameter page is to be determined (tbd). the timing associated wi th the bus cycles for the read parameter page command is defined elsewhere in the jedec standard. the read id command is used by the controller to identify the device that is attached. this command is used by the controller to gather information about the target flash device. figure 56 defines the behavior and timings. figure 56. de vice identification table read timing dq[7:0] r/ b t wb t r ech r-data 40h t rr
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 65 5.3.4. device identifi cation table definition table 44 defines the parameter page data structure. for pa rameters that span multiple bytes, the least significant byte of the parameter corresponds to the first byte. values are reported in the parameter page in units of by tes when referring to items related to the size of data access (as in an 8-bit data access device). for example, th e target will return how many data bytes are in a page. all optional parameters that are not implemen ted shall be cleared to 00h by the target. table 44 parameter page definitions byte o/m description value revision information and features block 0-3 m parameter page signature byte 0: ?j? (= 4ah) byte 1: ?e? (= 45h) byte 2: ?s? (= 53h) byte 3: ?d? (= 44h) 4ah, 45h, 53h, 44h 4-5 m revision number 2-15: reserved (0) 1: 1 = supports revision 1.0 0: reserved (0) 02h, 00h 6-31 reserved (0) all 00h manufacturer information block 32-43 m device manufacturer (12 ascii characters) toshiba 54h, 4fh, 53h, 48h 49h, 42h, 41h, 20h 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) tc58teg5dcjta00(TC58TEG5DCJTAI0) 54h, 43h, 35h, 38h 54h, 45h, 47h, 35h 44h, 43h, 4ah, 54h 41h, 30h(49h), 30h, 20h 20h, 20h, 20h, 20h 64-69 m jedec manufacturer id (6 bytes) 98h, 00h, 00h, 00h, 00h, 00h 70-79 reserved (0) all 00h memory organization block 80-83 m number of data bytes per page 00h, 40h, 00h, 00h 84-85 m number of spare bytes per page 00h, 05h 86-91 reserved (0) all 00h 92-95 m number of pages per block 00h, 01h, 00h, 00h 96-99 m number of blocks per logical unit (lun) 24h, 04h, 00h, 00h 100 m number of logical units (luns) 01h memory organization block 101 m number of address cycles 4-7: column address cycles 0-3: row address cycles 23h 102 m number of bits per cell 02h 103 reserved (0) all 00h 104 m multi-plane addressing 4-7: reserved (0) 0-3: number of plane address bits 00h 105-143 reserved (0) all 00h electrical parameters block 144-145 reserved (0) all 00h 146-147 o toggle ddr speed grade 5-15: reserved (0) 4: 1 = supports 10 ns speed grade (~100 mhz) 3: 1 = supports 12 ns speed grade (~83 mhz) 2: 1 = supports 15 ns speed grade (~66 mhz) 1: 1 = supports 25 ns speed grade (40 mhz) 1fh, 00h
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 66 0: 1 = supports 30 ns speed grade (~33 mhz) 148-150 reserved (0) all 00h 151 o toggle ddr features 0-7: reserved (0) 00h 152-168 reserved (0) all 00h 169 m driver strength support 2-7: reserved (0) 1: 1 = supports overdrive 1 drive strength 0: 1 = supports driver strength settings 03h 170-207 reserved (0) all 00h ecc and endurance block 208-419 reserved (0) all 00h vendor specific block 420-511 vendor specific vendor specific redundant parameter pages 512-1023 value of bytes 0-511 value of bytes 0-511 1024-1535 value of bytes 0-511 value of bytes 0-511
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 67 byte 0-3: parameter page signature this field contains the parameter page signature. when two or more bytes of the signature are valid, then it denotes that a valid copy of the parameter page is present. byte 0 shall be set to 4ah. byte 1 shall be set to 45h. byte 2 shall be set to 53h. byte 3 shall be set to 44h. byte 4-5: revision number this field indicates the revisions of the standard that the target complies to. the target may support multiple revisions of the standard. this is a bit field where each defined bit corresponds to a particular specification revision that the target may support. bit 0 shall be cleared to zero. bit 1 when set to one indicates that the target supports revision 1.0. bits 2-15 are reserved and shall be cleared to zero. byte 32-43: device manufacturer this field contains the manufacturer of the device. the content of this field is an ascii character string of twelve bytes. the device shall pad the character string with spaces (20h), if necessary, to ensure that the string is the proper length. there is no standard for how the manufacturer represents th eir name in the ascii string . if the host requires use of a standard manufacturer id, it should use the jedec manufacturer id. byte 44-63: device model this field contains the model number of the device. the conten t of this field is an ascii character string of twenty bytes. the device shall pad the character string with spaces (20h), if necessary, to ensure that the string is the proper length. byte 64-69: jedec manufacturer id this field contains the jedec manufacturer id for the manufacturer of the device. byte 80-83: number of data bytes per page this field contains the number of data bytes per page. the value reported in th is field shall be a power of two. the minimum value that shall be reported is 512 bytes. byte 84-85: number of spare bytes per page this field contains the number of spare bytes per page. there are no restrictions on the value. byte 92-95: number of pages per block this field contains the number of pages per block. byte 96-99: number of blocks per logical unit this field contains the number of blocks per logical uni t. there are no restrictions on this value. byte 100: number of logical units (luns) this field indicates the number of logical units the target supports. logical unit numbers are sequential, beginning with a lun address of zero. this field shall be greater than zero. byte 101: number of address cycles this field indicates the number of a ddress cycles used for row and column addresses. the reported number of address cycles shall be used by the host in operations that requir e row and/or column addresses (e.g. page program). bits 0-3 indicate the number of address cycles used for th e row address. this field shall be greater than zero. bits 4-7 indicate the number of address cycles used for the column address. this field sh all be greater than zero.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 68 note : throughout these standard examples are shown with 2-byte column addresses and 3-byte row addresses. however, the host is responsible for providing the numbe r of column and row address cycles in each of these sequences based on the va lues in this field. byte 102: number of bits per cell this field indicates the number of bits per cell in the flash array. this field shall be greater than zero. byte 104: multi-plane addressing this field describes parameters fo r multi-plane addressing. bits 0-3 indicate the number of bits that are used for plane addresses. this value shall be greater than 0h when multi-plane operations are supported. bits 4-7 are reserved. byte 146-147: toggle ddr1.0 speed grade this field indicates the toggle ddr1.0 speed grades supported. the target sha ll support an inclusive range of speed grades. bit 0 when set to one indicates that the target supports the 30 ns speed grade (~33 mhz). bit 1 when set to one indicate s that the target supports the 25 ns speed grade (40 mhz). bit 2 when set to one indicates that the target supports the 15 ns speed grade (~66 mhz). bit 3 when set to one indicates that the target supports the 12 ns speed grade (~83 mhz). bit 4 when set to one indicates that the target supports the 10 ns speed grade (~100 mhz). bit 5 when set to one indicates that the target supports the 7.5 ns speed grade (~133 mhz). bit 6 when set to one indicates that the target supports the 6 ns speed grade (~166 mhz). bit 7 when set to one indicates that the target supports the 5 ns speed grade (~200 mhz). bits 8-15 are reserved and shall be cleared to zero. byte 151: toggle ddr features this field describes features and attributes for toggle dd r1.0 operation. this byte is mandatory when the toggle ddr data interface is supported. bits 0-7 are reserved. byte 169: driver strength support this field describes if the target supports configurable driver strengths and its associated features. bit 0 when set to one indicates that th e target supports configurabl e driver strength settings as defined in table tbd. if this bit is set to one, then th e device shall support both the nominal an d underdrive settings. if this bit is set to one, then the device shall power-on with a driver strength at th e nominal value defined in table tbd. if this bit is cleared to zero, then the driver strength at power-on is undefined. this bit shall be set to one for devices that support the synchronou s ddr or toggle ddr data interface. bit 1 when set to one indicates that the target supports the ov erdrive 1 setting in table tbd for use in the i/o drive strength setting. this bit shall be set to one for devices that support the synchronous ddr or toggle ddr data interface. bits 2-7 are reserved. byte 420-511: vendor specific this field is reserved for vendor specific use.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 69 byte 512-1023: redundant parameter page 1 this field shall contain the values of bytes 0-511 of the parameter page. byte 512 is the value of byte 0. the redundant parameter page is used when the integrity crc indi cates that there was an error in bytes 0-511. the redundant parameter page shall be stored in non-vola tile media; the target shall not create these bytes by retransmitting the first 512 bytes. byte 1024-1535: redundant parameter page 2 this field shall contain the values of bytes 0-511 of the parameter page. byte 1024 is the value of byte 0. the redundant parameter page is used when the integrity crc indicates that there was an error in bytes 0-511 and in the first redundant parameter page. the redundant parame ter page shall be stored in non-volatile media; the target shall not create these bytes by retransmitting the first 512 bytes.
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 70 5.3.5. read status enhanced read status enhanced function is used to check status of selected lun and plane specif ied by row address setting. thus, the function requires row address se tting steps before reading status value. table 45 defines status values of each operation and figure 57 defines read status enha nced b ehavior and timings. table 45 read status enhanced definition dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 definition of value pass : "0" fail : "1" pass : "0" fail : "1" reserved reserved reserved busy : "0" ready : "1" busy : "0" ready : "1" protected : ?0? not protected : ?1? block erase pass/fail not use not use not use not use not use ready/busy write protect page program pass/fail not use not use not use not use not use ready/busy write protect cache program pass/fail for the current page pass/fail for the previous page not use not use not use busy/ready for flash array ready/busy for host write protect read not use not use not use not use not use not use ready/busy write protect cache read not use not use not use not use not use busy/ready for flash array ready/busy for host write protect copy-back pass/fail not use not use not use not use not use ready/busy write protect note: 1) during block erase, page program or copy-back operation, dq 0 is on ly valid when dq6 shows the ready state. 2) during cache program operation, dq 0 is only valid when dq 5 shows the ready state, and dq 1 is only valid when dq 6 shows the ready state. figure 57. read status timing sr[x] r1 r2 r3 78h t whr dq[7:0]
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 71 5.3.6. read lun #0 status operation read lun#0 status provides status value of lun#0 with out address setting. the function retrieves plane0 and plane1 status only. table 46 defines the status values and figure 58 defines read lun#0 status behavior and timing s. table 46 read lun#0 status definition dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 definition of value pass : "0" fail : "1" pass : "0" fail : "1" pass : "0" fail : "1" pass : "0" fail : "1" pass : "0" fail : "1" busy : "0" ready : "1" busy : "0" ready : "1" protected : "0" not protected : "1" block erase pass/fail for lun#0 pass/fail for plane#0 pass/fail for plane#1 not use not use not use ready/busy write protect page program pass/fail for lun#0 pass/fail for plane#0 pass/fail for plane#1 not use not use not use ready/busy write protect cache program pass/fail for lun#0 pass/fail for plane#0 (n) pass/fail for plane#1(n) pass/fail for plane#0 (n-1) pass/fail for plane#1(n-1) busy/ready for flash array ready/busy for host write protect read not use not use not use not use not use not use ready/busy write protect cache read not use not use not use not use not use busy/ready for flash array ready/busy for host write protect copy-back pass/fail for lun#0 pass/fail for plane#0 pass/fail for plane#1 not use not use not use ready/busy write protect note: 1) during block erase, page program or copy-back operation, dq 0, dq 1 and dq 2 are only valid when dq6 shows the ready state. 2) during cache program operation, dq 0, dq 1 and dq 2 ar e only valid when dq 5 sh ows the ready state, and dq 3 and dq 4 are only valid when dq 6 shows the ready state. figure 58. read lun#0 status timing sr[x] f1h t whr dq[7:0]
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 72 6. application notes and comments (1) prohibition of unspecified commands input of a command other than thos e specified in this document is prohibited. stored data may be corrupted if an unknown command is entered during the command cycle. (2) restriction of commands while in the busy state during the busy state, do not input an y command except 70h, 71h, 78h, f1h and ffh. (3) acceptable commands after serial input command ?80h? once the serial input command ?80h ? has been input, do not input any command other than the multi page program command "81h", the random data in put command ?85h?, multi page program command ?11h?, cache program command ?15h ?, the reset command ?ffh?, or read status commands until page program command ?10h? is input. if a command other than ?81h?, ?85h?, ?11h? , ?15h?, ?ffh?, or read st atus command is input, the program operation is not performed and the device operation is set to the mode which the input command specifies. (4) addressing for program operation within a block, the pages must be programmed consecut ively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the bl ock. random page address programming is prohibited. command other than ?81h?, ?85h?, ?11h? , ?15h? or ?ffh? 80 programming cannot be executed. 10 xx mode specified by the command. we by/ry 80 ff address input data in: data (1) page 0 data register page 2 page 1 page 31 page 255 (1) (2) (3) (32) (256) data (256) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 31 page 255 (2) (32) (3) (1) (256) data (256) ex.) random page program (prohibition)
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 73 (5) programming failure (6) by/ry : termination for the ready/busy pin ( by/ry ) a pull-up resistor needs to be used for termination because the by/ry buffer consists of an open drain circuit. fail 80 10 80 10 address m data input 70 i/o address n data input if the programming result for page address m is fail, do not try to program the page to address n in another block without the data input sequence. because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 80 m n this data may vary fr om device to device. we recommend that you use this data as a reference when selecting a resistor value. v cc v cc device v ss r by/ry c l 1.5 ? s 1.0 ? s 0.5 ? s 0 1 k ? 4 k ? 3 k ? 2 k ? 15 ns 10 ns 5 ns t f t r r t r t f v cc ? 3.3 v ta ? 25c c l ? 50 pf t f ready v cc 1.0 v t r 3.0 v 1.0 v busy
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 74 (7) when six address cycles are input although the device may read in a sixth address, it is ignored inside the chip. read operation program operation (8) several programming cycles on the same page (partial page program) this device does not support partial page programming. cle address input 00h ce we ale dqx by/ry ignored 30h cle ce we ale address input ignored 80h data input dqx
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 75 (9) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: at the time of shipment, the bad bl ock information is marked on each bad block. please do not perform an erase operation to bad blocks. it may be impossible to recover the bad block information if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the perfor mance of good blocks because it is isolated from the bit lines by select gates. refer to section 2.8 for the number of valid blocks over the device lifetime. (10) failure phenomena for prog ram and erase operations the device may fail during a program or erase operation. the following possible failure modes should be consid ered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase ? block replacement page programming failure status read after program ? block replacement random bit programming failure ?1 to 0? ecc ? ecc: tbd ? block replacement program erase when an error occurs during an erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). bad block bad block block a block b error occurs buffer memory
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 76 (11) do not turn off the power before write/erase operation is complete. avoid using th e device when the battery is low. power shortage and/or power failure before wr ite/erase operation is complete will cause loss of data and/or damage to data. (12) if ff reset command is input before completion of writ e operation to page b, it may cause damage to data not only to the programmed page, but also to the adjacent page a as follows. page a page b page a page b 0 2 1 4 3 6 5 8 225 228 7 10 227 230 9 12 229 232 11 14 231 234 13 16 233 236 15 18 235 238 17 20 237 240 19 22 239 242 21 24 241 244 23 26 243 246 25 28 245 248 27 30 247 250 249 252 251 254 253 255 (13) reliability guidance this reliability guidance is intended to notify some guidance related to using mlc nand flash with tbd. for detailed reliability data, please refer to toshiba?s reliability note. although random bit errors may occur during use, it does not necessarily mean that a block is bad. generally, a block should be marked as bad when a progra m status failure or erase st atus failure is detected. the other failure modes may be recovered by a block erase. ecc treatment for read data is mandatory due to the following data retention and read disturb failures. ? write/erase endurance write/erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either a program or a block er ase operation. the cumulative bad bl ock count will increase along with the number of write/erase cycles. ? data retention the data in memory may change after a certain amount of storage time. this is due to charge loss or charge gain. after block erasure and reprogramming, the block may become usable again. here is the combined characteristics image of write/erase endurance and data retention. write/erase endurance [cycles] data retention [years]
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 77 ? read disturb a read operation may disturb the data in memory. the da ta may change due to charge gain. usually, bit errors occur on other pages in the block, not the page being re ad. after a large number of re ad cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. after block erasure and reprogramming, the block may become usable again. (14) randomizing function controller shall employ randomizing func tion. all the columns with in a page shall be filled with randomized data at programming
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 78 7. package dimensions
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 79 8. revision history date rev. description 2012-01-26 0.0 initial issue 2012-01-30 0.1 clarification for the requirement of randomizing. deleted the definition of ov erdrive2 and odt behavior. 2012-03-01 0.2 added the definition of trw and trhw. integrated sdr ac timing table updated data transfer rate corrected 6 th cycle data of 40h address id de finition in read id operation. clarification for the address setting on random cache read operation clarification for the requirement of randomizing
toshiba confidential tc58teg5dcjtax0 tentative 2012-03-01c 80 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software an d systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situat ions in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, cu stomers must also refer to and comply with (a) the latest ve rsions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and applicat ion notes for product and the precautions and condi tions set forth in the "toshiba se miconductor reliability handbook" and (b) the instructions for the application with which the product will be us ed with or for. customers are solely responsible for all aspe cts of their own product design or applications , including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in c harts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operatin g parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specific applications as expressl y stated in this document. product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic s ignaling equipment, equipment used to control combustions or explosions, safety devices, elevat ors and escalators, devices related to el ectric power, and equipment used in finance-related fields. do not use product for unintended use unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no re sponsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this documen t, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related so ftware or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical , or biological weapons or missi le technology products (mass destruction w eapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. expor t administration regulations. ex port and re-export of product or related software or technology are strictly prohibited exc ept in compliance with all applicable export laws and regulations. ? product is subject to foreign ex change and foreign trade control laws. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result o f noncompliance with applicable laws and regulations.

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